`timescale 1ns / 1ps

module PC(
    input clk,
    input reset,
    input en,
    input [31:0] NPC,
    output reg[31:0] addr
    );

    initial addr <= 32'h0000_3000;

    always @(posedge clk) 
        if(reset) addr <= 32'h0000_3000;
        else if(en) addr <= NPC;

endmodule
